Computer graphics workstations can provide highly detailed grapghics simulations for a variety of applications. Engineers and designers working in the computer aided design (CAD) and computer aided manufacturing (CAM) areas typically utilize graphics simulations for a variety of computational tasks. The computer graphics workstation industry has thus been driven to provide more powerful computer graphics workstations which can perform graphics simulations quickly and with increased detail.
Modern workstations having graphics capabilities generally utilize "window" systems to accomplish graphics manipulations. As the industry has been driven to provide faster and more detailed graphics capabilities, computer workstation engineers have tried to design high performance, multiple window systems which maintain a high degree of user interactivity with the graphics workstation.
A primary function of window systems in such graphics workstations is to provide the user with simultaneous access to multiple processes on the workstation. Each of these processes provides an interface to the user through its own area onto the workstation display. The overall result for the user is an increase in productivity since the user can then manage more than one task at a time with multiple windows displaying multiple processes on the workstation.
In graphics systems, some scheme must be implemented to "render" or draw graphics primitives to the system's screen. "Graphics primitives" are a basic component of a graphics picture, such as a polygon or vector. All graphics pictures are formed with combinations of these graphics primitives. Many schemes may be utilized to perform graphics primitives rendering. One such scheme is the "spline tessellation" scheme utilized in the TURBO SRX graphics system provided by the Hewlett Packard Graphics Technology division, Fort Collins, Colorado.
The graphics rendering procedure generally takes place within a piece of graphics rendering hardware called a "frame buffer." A frame buffer generally comprises a plurality of video random access memory (VRAM) computer chips which store information concerning pixel activation on the system's display screen corresponding to the particular graphics primitives which will be traced out on the screen. Generally, the frame buffer contains all the graphics data information which will be written onto the windows and stores this information until the graphics system is prepared to trace this information on the workstation's screen. The frame buffer is generally dynamic and is periodically refreshed until the information stored in it is written to the screen.
Thus, computer graphics systems convert image representations stored in the computer's memory to image representations which are easily understood by humans. The image representations are typically displayed on a cathode ray tube (CRT) device that is divided into arrays of pixel elements which can be stimulated to emit a range of colored light. The particular color of light that a pixel emits is called its "value." Display devices such as CRTs typically stimulate pixels sequentially in some regular order, such as left to right and top to bottom, and repeat the sequence 50 to 70 times a second to keep the screen refreshed. Thus, some mechanism is required to retain a pixel's value between the times that this value is used to stimulate the display. The frame buffer is typically used to provide this "refresh" function.
Frame buffers, or "display processors," for displaying data in windows on display screens in graphics rendering systems are known in the art. For example, Randall discloses in U.S. Pat. No. 4,780,709, a display processor which divides a display screen such as a CRT into a plurality of horizontal strips, with each strip being further subdivided into a plurality of "tiles." Each tile represents a portion of a window to be displayed on the screen, and each tile is further defined by tile descriptors which include memory address locations of data to be displayed in that particular tile (col. 2, lines 23-35).
Since frame buffers are usually implemented as arrays of VRAMs, they are "bit mapped" such that pixel locations on a display device are assigned x,y coordinates of the frame buffer. A single VRAM device rarely has enough storage locations to completely store all the x,y coordinates corresponding to pixel locations for the entire image on a display device, and therefore, multiple VRAMs are generally used. The particular mapping algorithm used is a function of various factors, such as what particular VRAMs are available, how quickly the VRAM can be accessed compared to how quickly pixels can be rendered, how much hardware it takes to support a particular mapping, and other factors.
Prior frame buffers in graphics systems comprised of VRAMs are generally dual port, random access memories. A serial output port develops the active video portion of a displayed video signal. Generally, signal processing circuitry accesses the VRAMs in the frame buffer via a standard input/output bus wherein the access is controlled by a VRAM control unit. As is known by those with skill in the art, data held in the VRAMs is provided to graphics processing circuitry which generally comprises decoders, first-in/first-out (FIFO) circuits, and an arithmetic and logic unit (ALU) as described, for example, in U.S. Pat. No. 4,816,913 to Harney et al.
Generated pixel value data are written to the VRAMs in the frame buffer via output FIFOs in matrix form. The matrix corresponds to lines of the video signal wherein each line has a separate number of pixel values. This matrix is referred to as the "bit map," and is read from the VRAMs by a graphics display processor to produce an image on the graphics system display device. Display processors provide horizontal line synchronizing signals and vertical field synchronizing signals to coordinate transfer of data from the VRAMs to the display processor for ultimate display on a CRT as described by Harney at col. 6, lines 7 through 24 of the aforementioned patent.
Generally, display devices in graphics systems are "raster scan" displays. Raster scan displays utilize a multiplicity of beams for simultaneously imaging data on a corresponding multiplicity of parallel scan lines. The multiplicity of beams usually write pixel value data to stimulate pixels on the display from the left side of the display CRT to the right side of the display CRT. For the purpose of dividing the CRT into tiles (a process called "tiling"), each tile is considered to comprise a depth equal to the multiplicity of scan lines, with each tile being a particular number of pixels wide. The resulting graphics primitive image thus comprises a multiplicity of parallel, non-overlapping sets of parallel lines of pixels generated by a separate sweep of electron beams across the CRT screen. The tiles are generally rectangular, and thus organize the image into arrays having a plurality of rows by a set number of columns.
Typically, raster scan displays are organized along scan lines wherein pixels in a display are activated according to the bit-mapped frame buffer coordinate pixel values. In this way, graphics primitives which potentially have random orientations and sizes are plotted on the raster display. The scanning raster CRT is accessed by the frame buffer according to row address strobe (RAS) and column address strobe (CAS) raster beams. Because of the basic random nature of graphics primitives, it is desirable from a systems standpoint to have longer distances between the RAS boundaries in the vertical direction. Prior graphics systems using frame buffers with VRAM architecture generally do not provide long distances between the RAS boundaries in the vertical direction. Thus, prior graphics systems do not solve a long-felt need in the art for systems which maximize page mode performance from VRAM arrays in the graphics subsystem.
Bit mapped systems generally utilize direct memory access (DMA) transfer sequences for transferring data from some external memory such as a ROM, cache buffer, or host processor to the VRAMs in the frame buffer. Thus, bit map systems are known which provide means for displaying characters and graphics patterns on CRT displays. For example, Ogawa et al. in U.S. Pat. No. 4,837,564 disclose such a system at col. 1, lines 17 through 40 thereof. In conventional graphics systems, DMA transfer control is performed independently of processing control of graphics primitives attributes. Since a large number of hardware components are generally necessary for realizing DMA control sequences, the circuitry for such systems is complicated and the processing speed for expanding display data in a VRAM array may be reduced. In such systems, total processing speed for DMA sequences is not satisfactorily increased thus (Ogawa et al., col. 1, lines 56 through 65). There is thus a long-felt need in the art for control data sequences for DMA transfer which increase processing speed and decrease the amount of expensive hardware necessary to perform this function.
When graphics primitives are rendered to a CRT a display refresh port receives an incrementing address from the frame buffer, and the output data is first buffered and then serialized using high speed shift registers typically built into the frame buffer architecture. The frame buffer then sends output data which drives digital to analog converters in a standard red/green/blue color monitor, or in a direct fashion to drive a black and white (monochrome) monitor. For example, such a system is described in U.S. Pat. No. 4,745,407 to Costello (col. 1, lines 32 through 55). A second update port, sometimes called a "random" port of the frame buffer is usually configured as an x,y random access memory wherein the frame buffer is organized into x,y coordinates.
Several schemes have been employed to facilitate DMA transfer in graphics systems. Such schemes involve bit-to-bit address control, built in vector generators, and all points addressable frame buffers with multiple axes and independent square access as described by way of example in U.S. Pat. No. 4,816,814 to Lumelsky (col. 2, line 63 through col. 3, line 2). However, these schemes fail to provide a solution to the aforementioned long-felt needs in the art since they generally require complicated hardware manipulation of addresses and data and do not provide adequate generation of graphics primitives on a display device. These systems also do not aid in maximizing the serial port (refresh) of a frame buffer, and thus, they do not maximize page mode performance for frame buffers comprising VRAM array architectures.
As is known by those with skill in the art, the process of scrolling an image, or a portion of an image on a display device, involves reading pixel data from one area of a frame buffer memory and writing the data to another area. Traditionally, frame buffer memories that perform this function have been arranged such that groups of pixels along scan lines are stored at sequentially addressed memory locations. By using FIFO buffers for storing several words of pixel data which have been read from sequential memory addresses, the scrolling speed may be improved since the addresses are rapidly incremented by a counter rather than by a host display processor or controller. Such a system is described by way of example in U.S. Pat. No. 4,755,810 Knierim. The Knierim patent discloses a FIFO buffer which is provided to store sequences of data from a frame buffer and which comprises a barrel shifter to shift bit positions of the data words stored in the FIFO to facilitate proper pixel alignment during the horizontal scrolling operation.
The use of a barrel shifter as disclosed in the Knierim patent improves page mode operation and performance in a frame buffer graphics system. However, further improvements with an eye toward maximizing page mode performance and column address coherency is desired in the art. This need must be satisfied without increasing the cost and complexity of the hardware necessary to form DMA transfer circuitry. The aforementioned long-felt needs are solved by methods and apparatus provided in accordance with the present invention.